In the last few years the endeavor has been to increase the efficiency of the above devices for increasing their breakdown voltage and reducing their output resistance.
U.S. Pat. Nos. 6,586,798 B1, 6,228,719 B1, 6,300,171 B1 and 6,404,010, all commonly assigned and incorporated by reference, describe methods for solving the problems set forth above. These patents describe power MOS devices comprising column structures having a first conductivity type (for example, a P type), spaced by epitaxial layer portions having a second conductivity type (here, an N type). Basically, in order to form the column structures, a plurality of epitaxial layers of N type are sequentially grown, each growth being followed by an implantation of dopant of P type. Stacking of the implanted regions thus forms column structures, which represents an extension of the body regions of the device within the epitaxial layer that constitutes the drain region of the device. The charge concentration of the dopant introduced via the implantations, i.e., the concentration of the column structures of P type thus formed, is equal to, but of opposite sign with respect to, the concentration of charge introduced epitaxially. Consequently, by virtue of the charge balance thus obtained, vertical-conduction power devices can be provided with high breakdown voltage and with low output resistance, on account of the high concentration of the epitaxial layer (MD technology).
In addition, it is also known that, by increasing the density of the elementary strips that form the device, i.e., by increasingly packing the device, it is possible to further increase the charge concentration of the epitaxial layer, obtaining devices which, given a same breakdown voltage (linked to the height of the columns), have increasingly lower output resistance.
On the other hand, however, in order to increase the density of the elementary strips of the device, one increases the number of steps of epitaxial growth and reduces the thermal change undergone by the device. This may bring about an increase in the device cost, in the cycle time, and in the defects created by the various steps of epitaxial growth. In particular, with reference to the latter problem, each defect left at the interface between one epitaxial layer and the subsequent one may render the device less efficient.
Moreover, solutions exist for obtaining charge balance by forming trenches and filling the trenches with successive polysilicon, thermal oxide, and deposited oxide layers. However, these solutions may not solve the problem of defectiveness.